1. Field of the Invention
This invention relates to a method of integration testing for packaged electronic components and particularly to a capability of technology to improve a conventional testing for packaged electronic components of the quad flat no-lead type (QFN). In this method, non-tested sides of the packaged electronic components are stuck with a downward exposure onto a testing carrier board so that conductive pins are oriented to test spaces to test the plurality of packaged components stuck onto the testing carrier board according to testing steps for convenient classification packaging, advanced testing efficiency, economical working hours and costs, simplified testing procedures, and raised efficiency, and thus the invention for an improvement of low cost and high efficiency may be used in most locations with production lines testing the packaged electronic components.
2. Description of Related Art
In a semiconductor manufacturing process, there are four flows divided into IC design, wafer fabrication (Wafer Fab), wafer probe, and wafer packaging. In wafer probe, each die on a chip is probed and a probe made of a gold wire as thin as hair is fit on a head of the detector contacts pad on the die to test for electrical characteristics. Unqualified dice are marked. Next, when the chip is cut into dice in units of die, marked die or dice are unqualified and eliminated and thus do not pass to a next process to avoid wasting manufacturing costs. Wafer packaging is the last process of the entire semiconductor manufacturing processes, mainly packaging a cut single IC with a mold.
To improve the performance of the production line for the testing of packaged electronic components is an item various wafer OEMs actively develop and build, and the technology, such as that for improving production flows, may be applicable in all kinds of locations to test packaged chips so as to reduce the manufacturing and working-hour costs. So far, to improve testing flow has been a very important item because a chip packaging testing machine is a much more precise machine, and thus even slight modifications of the machine are always expensive. Peripheral flows, however, may be improved matching with indigenous features of machines for producing a marked effect with relative lower cost. In particular, before and after the packaging process, the characteristics of chip may be impacted and part of the wafer to be tested is guaranteed in quality. The testing must thus be performed for leveling after packaging process, and chip circuits that are slightly different from each other in a series of products or chip circuits of different products at the time of layout usually may be laid on the same piece of wafer, so a fast, efficient method of leveling a product testing must be found for the packaged electronic components after cutting and packaging, regardless of their quality or product classification.
Generally known packaging types are divided into dual in-line package (DIP), chip size package (CSP), small outline package (SOP), quad flat no-lead (QFN, same as dual flat no-lead (DFN) in series) package, plastic leaded chip carrier (PLCC) package, ball grid array (BGA) package, and special FCP. Various customized packages are being developed as well. Generalized semiconductor packages also comprise an LED sensor and a specific IC package, and applications in different fields depend on demands of different industries and characteristics of semiconductor elements.
FIG. 1A is a view of a bottom-surface QFN package and FIG. 1B is a view of a DFN package; a conventional packaged structure of packaged electronic component described herein generally has a top side commonly provided with no circuit contacts that may be lateral leads or contacts and also bottom-surface contacts (seen as 4 rows of blocks in FIG. 1A and as 2 rows of blocks in FIG. 1B); however, before a testing of the electronic component after packaging is performed, separate small grains of chips must be mounted, which is, generally speaking, a complicated flow. The testing flow in particular runs slower.